A method based on the branch-and-bound algorithm capable of generating all possible solutions to find the best one is proposed for analog function blocks. Since the method has some drawbacks, constraints are classified into two groups; constraints on single side and constraints between two nets. Thus, the method has two parts; (a) only constraints on single nets are processed and (b) only constraints between two nets are processed. Due to the fact that many possible routes that violate layout constraints are rejected immediately in each part, the method can be efficient. In fact, experimental results indicate that the proposed method is capable of finding a good global route for hard layout constraints in practical processing time and also show that it is superior to the well-known simulated annealing method in quality of solutions and in processing time.
|ジャーナル||IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences|
|出版ステータス||Published - 1995 3 1|
ASJC Scopus subject areas
- コンピュータ グラフィックスおよびコンピュータ支援設計