抄録
An LSI compaction method which minimizes total wire length as well as layout area is discussed. First, the compaction problem is formulated as a linear programming problem and reduced to a problem involving finding a tree which has some properties in a constraint graph. Then, a method which finds the tree by a sequence of elementary tree transformations in the graph is proposed. It corresponds to the primal simplex method for LP. However, the proposed method is much more efficient, because it does not deal with any matrices in solving the problem.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings - IEEE International Symposium on Circuits and Systems |
| 出版社 | IEEE |
| ページ | 1455-1458 |
| ページ数 | 4 |
| 出版ステータス | Published - 1985 |
| 外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学
- 電子材料、光学材料、および磁性材料