Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint

Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto

研究成果: Article

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With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 ̃ 50%.

元の言語English
ページ(範囲)2482-2489
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
発行部数12
DOI
出版物ステータスPublished - 2011 12

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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