抄録
With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 ̃ 50%.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 2482-2489 |
| ページ数 | 8 |
| ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻 | E94-A |
| 発行部数 | 12 |
| DOI | |
| 出版物ステータス | Published - 2011 12 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
これを引用
Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint. / Sode Tanaka, Mikiko; Togawa, Nozomu; Yanagisawa, Masao; Goto, Satoshi.
：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E94-A, 番号 12, 12.2011, p. 2482-2489.研究成果: Article
}
TY - JOUR
T1 - Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint
AU - Sode Tanaka, Mikiko
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Goto, Satoshi
PY - 2011/12
Y1 - 2011/12
N2 - With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 ̃ 50%.
AB - With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 ̃ 50%.
KW - Circuit simulation
KW - Power distribution network
KW - Power supply noise
KW - Signal integrity
UR - http://www.scopus.com/inward/record.url?scp=82655162916&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=82655162916&partnerID=8YFLogxK
U2 - 10.1587/transfun.E94.A.2482
DO - 10.1587/transfun.E94.A.2482
M3 - Article
AN - SCOPUS:82655162916
VL - E94-A
SP - 2482
EP - 2489
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -