For low power consumption which makes more than doubles a battery life, the charge-recycling system by reuse the energy between the two or more CPUs and the task scheduling technique for high efficiency are proposed. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. To control divided loads, a high speed and efficient regulator are needed. The internal circuit voltage variation between upper and lower modules is solved by seven LDO regulators, boosting switched capacitor and the tank capacitor. As a result, the stable voltage can be supplied to each CPU, even if upper and lower loads are different or battery is used. The LDOs improve the margin of accumulation of tank capacitor or task schedule operation, and the power efficiency is raised further. The system can be on-chip without external large control circuit and inductor like switching regulator. The test chips were fabricated using 90nm standard CMOS technology. Although the power efficiency of the conventional system with a simple LDO is 44.4% at the maximum, that of the proposed charge-recycling system improves to 88.9%.
|ホスト出版物のタイトル||Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC|
|出版ステータス||Published - 2012|
|イベント||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe|
継続期間: 2012 11月 12 → 2012 11月 14
|Other||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|Period||12/11/12 → 12/11/14|
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