This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted, to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 μm technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC, codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding.