Hardware architecture design of CABAC Codec for H.264/AVC

Lingfeng Li*, Yang Song, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted, to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 μm technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC, codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding.

本文言語English
ホスト出版物のタイトル2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOI
出版ステータスPublished - 2007 9 28
イベント2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan, Province of China
継続期間: 2007 4 252007 4 27

出版物シリーズ

名前2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
国/地域Taiwan, Province of China
CityHsinchu
Period07/4/2507/4/27

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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