Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

19 引用 (Scopus)

抜粋

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

元の言語English
ホスト出版物のタイトルGLSVLSI'07
ホスト出版物のサブタイトルProceedings of the 2007 ACM Great Lakes Symposium on VLSI
ページ160-163
ページ数4
DOI
出版物ステータスPublished - 2007 10 1
イベント17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
継続期間: 2007 3 112007 3 13

出版物シリーズ

名前Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference17th Great Lakes Symposium on VLSI, GLSVLSI'07
Italy
Stresa-Lago Maggiore
期間07/3/1107/3/13

ASJC Scopus subject areas

  • Engineering(all)

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  • これを引用

    Liu, Z., Huang, Y., Song, Y., Goto, S., & Ikenaga, T. (2007). Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. : GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI (pp. 160-163). [1228826] (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1228784.1228826