A hardware speech codec that is based on an adaptive predictive coding with maximum-likelihood quantization (APC-MLQ) algorithm capable of alternating the coding rates between 9. 6 kb/s and 16 kb/s is described. The codec is implemented on printed circuit boards that include analog interfaces, 64 kb/s PCM interfaces, sampling-rate converters between 8 and 6. 4 kHz, an APC-MLQ coder, and a decoder. Eight T1 TMS 32010 DSP chips are used to construct the codec. Extensive efforts have been made to reduce the processing delay, resulting in a total codec delay of 65 ms at 9. 6 kb/s and 63 ms at 16 kb/s. The major analog characteristics meet the specifications of CCITT G. 712 for 64 kb/s PCM at both transmission rates. The codec provides high speech quality not ony at 16 kb/s but also at 9. 6 kb/s, which is sufficient for mobile satellite communications. The 16 kb/s codec can maintain the transparency of voiceband data at 2. 4 kb/s or below.
|ジャーナル||Conference Record - International Conference on Communications|
|出版ステータス||Published - 1987|
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering