Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems

Krzysztof Jozwik*, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In the field of embedded systems, where ever-growing demands for short time-to-market, low cost, low power, high performance and increased flexibility are prevalent, modern FPGAs (Field Programmable Gate Arrays) are gaining wider popularity in a variety of applications. Moreover, capability of DPR (Dynamic Partial Reconfiguration) found in some of these devices can further help in meeting these demands. With the increasing trend to integrate multiple functions into a single device, programming difficulty, well known for FPGAs, and the complexity of management of dynamically reconfigurable resources drive the need for an OS (Operating System). The OS would provide a well-defined computing model abstracting details and capacity of the underlying hardware. This paper familiarizes the readers with the topic of DPR, pointing out its advantages and limitations, and a related HW (hardware) multitasking computing model. Furthermore, it presents results of an ongoing research on an efficient hardware platform for HW multitasking and an accompanying OS extension which facilitates its programmability and serves as a base for fully fledged DPR embedded systems.

本文言語English
ホスト出版物のタイトル2011 International SoC Design Conference, ISOCC 2011
出版社IEEE Computer Society
ページ183-186
ページ数4
ISBN(印刷版)9781457707100
DOI
出版ステータスPublished - 2011
イベント8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of
継続期間: 2011 11月 172011 11月 18

出版物シリーズ

名前2011 International SoC Design Conference, ISOCC 2011

Conference

Conference8th International SoC Design Conference 2011, ISOCC 2011
国/地域Korea, Republic of
CityJeju
Period11/11/1711/11/18

ASJC Scopus subject areas

  • 電子工学および電気工学
  • ハードウェアとアーキテクチャ

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