Hardware optimizations of variable block size hadamard transform for H.264/AVC FREXT

Zhenyu Liu, Dongsheng Wang, Takeshi Ikenaga

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

Variable block size (VBS) transform technique is adopted in Fidelity Range Extensions (FRExt) of H.264/AVC, in which 8 x 8/4 x 4 Hadamard transforms are adaptively employed during the fractional motion estimation. The hardwired VBS Hadamard transform unit is developed by authors and the following contributions are described in this literature: (1) Hardware reusing scheme is adopted in the architecture design; (2) In the light of the noise analysis, the intermediate data bit-truncation scheme is developed to reduce the hardware cost while maintaining its computational precision well; (3) With mathematical analysis, the bit-width of SATD value is reduced as compared to the intuitive implementation, therefore, the power and hardware cost are both optimized for the SATD generator implementation; (4) Hybrid 4:2/3:2 compressor based CSA tree is analyzed in the circuits design of SATD generator; and (5) Clock-gating technique is employed to reduce the power dissipation of 4x4 transform operation. With TSMC 0.18μm CMOS technology, experimental results reveal that 12.2-30.4% saving in hardware cost and 12.4-32.4% saving in power consumption are achieved by using our algorithms.

本文言語English
ホスト出版物のタイトル2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings
出版社IEEE Computer Society
ページ2701-2704
ページ数4
ISBN(印刷版)9781424456543
DOI
出版ステータスPublished - 2009 1 1
イベント2009 IEEE International Conference on Image Processing, ICIP 2009 - Cairo, Egypt
継続期間: 2009 11 72009 11 10

出版物シリーズ

名前Proceedings - International Conference on Image Processing, ICIP
ISSN(印刷版)1522-4880

Conference

Conference2009 IEEE International Conference on Image Processing, ICIP 2009
国/地域Egypt
CityCairo
Period09/11/709/11/10

ASJC Scopus subject areas

  • ソフトウェア
  • コンピュータ ビジョンおよびパターン認識
  • 信号処理

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