### 抜粋

In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

元の言語 | English |
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ページ（範囲） | 2338-2346 |

ページ数 | 9 |

ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

巻 | E82-A |

発行部数 | 11 |

出版物ステータス | Published - 1999 1 1 |

外部発表 | Yes |

### ASJC Scopus subject areas

- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics

## フィンガープリント Hardware synthesis from C programs with estimation of bit length of variables' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

## これを引用

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E82-A*(11), 2338-2346.