Hardware synthesis from C programs with estimation of bit length of variables

Osamu Ogawa, Kazuyoshi Takagi, Yasufumi Itoh, Shinji Kimura, Katsumasa Watanabe

研究成果: Article

5 引用 (Scopus)

抄録

In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

元の言語English
ページ(範囲)2338-2346
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
発行部数11
出版物ステータスPublished - 1999
外部発表Yes

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Hardware
Synthesis
Compiler
High level languages
Networks (circuits)
Adders
Estimation Algorithms
Data Flow
Optimization Methods
Path
Unit
Necessary
Optimization
Graph in graph theory
Experiments
Experiment
Language

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

これを引用

Hardware synthesis from C programs with estimation of bit length of variables. / Ogawa, Osamu; Takagi, Kazuyoshi; Itoh, Yasufumi; Kimura, Shinji; Watanabe, Katsumasa.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E82-A, 番号 11, 1999, p. 2338-2346.

研究成果: Article

Ogawa, Osamu ; Takagi, Kazuyoshi ; Itoh, Yasufumi ; Kimura, Shinji ; Watanabe, Katsumasa. / Hardware synthesis from C programs with estimation of bit length of variables. :: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 1999 ; 巻 E82-A, 番号 11. pp. 2338-2346.
@article{1de3caf173374c73824027dd84902c0e,
title = "Hardware synthesis from C programs with estimation of bit length of variables",
abstract = "In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.",
keywords = "C language, Compiler, Hardware/software codesign, High-level synthesis, VHDL",
author = "Osamu Ogawa and Kazuyoshi Takagi and Yasufumi Itoh and Shinji Kimura and Katsumasa Watanabe",
year = "1999",
language = "English",
volume = "E82-A",
pages = "2338--2346",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - Hardware synthesis from C programs with estimation of bit length of variables

AU - Ogawa, Osamu

AU - Takagi, Kazuyoshi

AU - Itoh, Yasufumi

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 1999

Y1 - 1999

N2 - In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

AB - In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

KW - C language

KW - Compiler

KW - Hardware/software codesign

KW - High-level synthesis

KW - VHDL

UR - http://www.scopus.com/inward/record.url?scp=0038469454&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038469454&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0038469454

VL - E82-A

SP - 2338

EP - 2346

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 11

ER -