This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.
|出版ステータス||Published - 1997 1 1|
|イベント||Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97 - Braunschweig, Ger|
継続期間: 1997 3 24 → 1997 3 26
|Other||Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97|
|Period||97/3/24 → 97/3/26|
ASJC Scopus subject areas
- Hardware and Architecture