Hardware/software codesign method for a general purpose reconfigurable co-processor

Shinji Kimura, Mitsuteru Yukishita, Yasufumi Itou, Akira Nagoya, Makoto Hirao, Katumasa Watanabe

研究成果: Paper査読

2 被引用数 (Scopus)

抄録

This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

本文言語English
ページ147-151
ページ数5
出版ステータスPublished - 1997 1 1
外部発表はい
イベントProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97 - Braunschweig, Ger
継続期間: 1997 3 241997 3 26

Other

OtherProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97
CityBraunschweig, Ger
Period97/3/2497/3/26

ASJC Scopus subject areas

  • Hardware and Architecture

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