HDTV1080p H.264/AVC encoder chip design and performance analysis

Zhenyu Liu*, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

*この研究の対応する著者

研究成果査読

68 被引用数 (Scopus)

抄録

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 $\mu\hbox{m}$ CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 $\hbox{mm}^{2}$ die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

本文言語English
論文番号4768914
ページ(範囲)594-608
ページ数15
ジャーナルIEEE Journal of Solid-State Circuits
44
2
DOI
出版ステータスPublished - 2009 2

ASJC Scopus subject areas

  • 電子工学および電気工学

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