TY - BOOK
T1 - Heterogeneous multicore processor technologies for embedded systems
AU - Uchiyama, Kunio
AU - Arakawa, Fumio
AU - Kasahara, Hironori
AU - Nojiri, Tohru
AU - Noda, Hideyuki
AU - Tawara, Yasuhiro
AU - Idehara, Akio
AU - Iwata, Kenichi
AU - Shikano, Hiroaki
N1 - Publisher Copyright:
© 2012 Springer Science+Business Media New York. All rights are reserved.
PY - 2012/10/1
Y1 - 2012/10/1
N2 - To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.
AB - To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.
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U2 - 10.1007/978-1-4614-0284-8
DO - 10.1007/978-1-4614-0284-8
M3 - Book
AN - SCOPUS:84949179289
SN - 1461402832
SN - 9781461402831
VL - 9781461402848
BT - Heterogeneous multicore processor technologies for embedded systems
PB - Springer New York
ER -