High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto

研究成果: Conference article査読

10 被引用数 (Scopus)

抄録

A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.

本文言語English
ページ(範囲)62-63
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 2000 1 1
外部発表はい
イベント2000 Symposium on VLSI Technology - Honolulu, HI, USA
継続期間: 2000 6 132000 6 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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