High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto

研究成果: Conference article

10 引用（Scopus）

フィンガープリント High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

Engineering & Materials Science

Physics & Astronomy