HIGH LATCH-UP IMMUNITY FULL CMOS RAM.

K. Anami*, M. Yoshimoto, T. Yoshihara, S. Nagao, Y. Akasaka, T. Nakano

*この研究の対応する著者

研究成果

2 被引用数 (Scopus)

抄録

Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - Symposium on VLSI Technology
Place of PublicationTokyo, Jpn
出版社Business Cent for Academic Soc Japan
ページ12-13
ページ数2
ISBN(印刷版)4930813085
出版ステータスPublished - 1984
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)

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