Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.
|ホスト出版物のタイトル||Digest of Technical Papers - Symposium on VLSI Technology|
|Place of Publication||Tokyo, Jpn|
|出版社||Business Cent for Academic Soc Japan|
|出版ステータス||Published - 1984|
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