抄録
This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| 出版場所 | Piscataway, NJ, United States |
| 出版者 | IEEE |
| ページ | 265-274 |
| ページ数 | 10 |
| 出版物ステータス | Published - 1998 |
| イベント | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn 継続期間: 1998 2 10 → 1998 2 13 |
Other
| Other | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
|---|---|
| 市 | Yokohama, Jpn |
| 期間 | 98/2/10 → 98/2/13 |
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ASJC Scopus subject areas
- Engineering(all)
これを引用
High-level synthesis system for digital signal processing based on enumerating data-flow graphs. / Togawa, Nozomu; Hisaki, Takafumi; Yanagisawa, Masao; Ohtsuki, Tatsuo.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 265-274.研究成果: Chapter
}
TY - CHAP
T1 - High-level synthesis system for digital signal processing based on enumerating data-flow graphs
AU - Togawa, Nozomu
AU - Hisaki, Takafumi
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 1998
Y1 - 1998
N2 - This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
AB - This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
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UR - http://www.scopus.com/inward/citedby.url?scp=0032218668&partnerID=8YFLogxK
M3 - Chapter
AN - SCOPUS:0032218668
SP - 265
EP - 274
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PB - IEEE
CY - Piscataway, NJ, United States
ER -