High-level synthesis with post-silicon delay tuning for RDR architectures

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In this paper, we propose a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.

本文言語English
ホスト出版物のタイトルISOCC 2013 - 2013 International SoC Design Conference
出版社IEEE Computer Society
ページ194-197
ページ数4
ISBN(印刷版)9781479911417
DOI
出版ステータスPublished - 2013 1 1
イベント2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
継続期間: 2013 11 172013 11 19

出版物シリーズ

名前ISOCC 2013 - 2013 International SoC Design Conference

Conference

Conference2013 International SoC Design Conference, ISOCC 2013
国/地域Korea, Republic of
CityBusan
Period13/11/1713/11/19

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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