High-parallel performance-aware LDPC decoder IP core design for WiMAX

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    3 被引用数 (Scopus)

    抄録

    In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.

    本文言語English
    ホスト出版物のタイトルMidwest Symposium on Circuits and Systems
    ページ1136-1139
    ページ数4
    DOI
    出版ステータスPublished - 2013
    イベント2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH
    継続期間: 2013 8 42013 8 7

    Other

    Other2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
    CityColumbus, OH
    Period13/8/413/8/7

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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