High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong, Yang Wang, Zhen Lin, Takahiro Watanabe

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

元の言語English
ホスト出版物のタイトルASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
ページ891-894
ページ数4
DOI
出版物ステータスPublished - 2009
イベント2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
継続期間: 2009 10 202009 10 23

出版物シリーズ

名前ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
China
Changsha
期間09/10/2009/10/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Dong, Y., Wang, Y., Lin, Z., & Watanabe, T. (2009). High performance and low latency mapping for neural network into network on chip architecture. : ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (pp. 891-894). [5351550] (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351550