High performance autoassociative neural network using network on chip

Yiping Dong*, Zhen Lin, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

抄録

In this paper, an Artificial Autoassociative Neural Network (AANN) is implemented by Network on Chip (NoC) architecture to solve communication and performance problem. This proposed NoC based system can map four neurons in one PE and the whole system consists of PEs each of which connects with a router. This system is reconfigurable and extendable so that it can easily suit for different applications. Simulation results show that the proposed implementation method can reduce communication load and total computation time.

本文言語English
ホスト出版物のタイトル2009 1st International Conference on Information Science and Engineering, ICISE 2009
ページ4015-4018
ページ数4
DOI
出版ステータスPublished - 2009 12月 1
イベント1st International Conference on Information Science and Engineering, ICISE2009 - Nanjing, China
継続期間: 2009 12月 262009 12月 28

出版物シリーズ

名前2009 1st International Conference on Information Science and Engineering, ICISE 2009

Conference

Conference1st International Conference on Information Science and Engineering, ICISE2009
国/地域China
CityNanjing
Period09/12/2609/12/28

ASJC Scopus subject areas

  • 情報システム

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