High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture

Changqi Yang*, Kouichi Kumagai, Yoshihiro Mabuchi, Kenji Yoshida, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

抄録

The high performance chip design on H.264/AVC integer motion estimation is presented in this paper to satisfy the requirements from real-time HDTV video applications. Using a novel multi-chip architecture named System in Silicon (SiS), core ASIC and external DRAMs which are designed in different design rules are integrated onto a single chip to achieve the significantly wide word-width of 1024 bits and band-width of 25Gbps in logic-memory communication. In core's design, 2D PE array is adopted to avoid the broadcast signals which limit the circuit's speed and the delay registers which prevent the full hardware utilization. As the implementation, this chip is fabricated with 0.18μm technology (core) and 0.11μm technology (DRAM). The core size is 14.1×7.1 mm2, it contains 1966.1K logic gates and 22.5KB SRAM. It can work at the high operating clock frequency up to 200MHz and can process more than 263K macro blocks within one second. It is suitable to the application of HDTV video streams (1920×1088) at real time (30fps) and can be a useful part of multimedia system.

本文言語English
ホスト出版物のタイトル25th PCS Proceedings
ホスト出版物のサブタイトルPicture Coding Symposium 2006, PCS2006
出版ステータスPublished - 2006
イベント25th PCS: Picture Coding Symposium 2006, PCS2006 - Beijing, China
継続期間: 2006 4月 242006 4月 26

出版物シリーズ

名前25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006
2006

Conference

Conference25th PCS: Picture Coding Symposium 2006, PCS2006
国/地域China
CityBeijing
Period06/4/2406/4/26

ASJC Scopus subject areas

  • 工学(全般)

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