High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture

Changqi Yang, Kouichi Kumagai, Yoshihiro Mabuchi, Kenji Yoshida, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

抄録

The high performance chip design on H.264/AVC integer motion estimation is presented in this paper to satisfy the requirements from real-time HDTV video applications. Using a novel multi-chip architecture named System in Silicon (SiS), core ASIC and external DRAMs which are designed in different design rules are integrated onto a single chip to achieve the significantly wide word-width of 1024 bits and band-width of 25Gbps in logic-memory communication. In core's design, 2D PE array is adopted to avoid the broadcast signals which limit the circuit's speed and the delay registers which prevent the full hardware utilization. As the implementation, this chip is fabricated with 0.18μm technology (core) and 0.11μm technology (DRAM). The core size is 14.1×7.1 mm2, it contains 1966.1K logic gates and 22.5KB SRAM. It can work at the high operating clock frequency up to 200MHz and can process more than 263K macro blocks within one second. It is suitable to the application of HDTV video streams (1920×1088) at real time (30fps) and can be a useful part of multimedia system.

元の言語English
ホスト出版物のタイトル25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006
2006
出版物ステータスPublished - 2006
イベント25th PCS: Picture Coding Symposium 2006, PCS2006 - Beijing
継続期間: 2006 4 242006 4 26

Other

Other25th PCS: Picture Coding Symposium 2006, PCS2006
Beijing
期間06/4/2406/4/26

Fingerprint

Motion estimation
High definition television
Dynamic random access storage
Silicon
Multimedia systems
Logic gates
Static random access storage
Application specific integrated circuits
Macros
Clocks
Hardware
Bandwidth
Data storage equipment
Networks (circuits)
Communication

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Yang, C., Kumagai, K., Mabuchi, Y., Yoshida, K., Ikenaga, T., & Goto, S. (2006). High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture. : 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006 (巻 2006)

High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture. / Yang, Changqi; Kumagai, Kouichi; Mabuchi, Yoshihiro; Yoshida, Kenji; Ikenaga, Takeshi; Goto, Satoshi.

25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006. 巻 2006 2006.

研究成果: Conference contribution

Yang, C, Kumagai, K, Mabuchi, Y, Yoshida, K, Ikenaga, T & Goto, S 2006, High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture. : 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006. 巻. 2006, 25th PCS: Picture Coding Symposium 2006, PCS2006, Beijing, 06/4/24.
Yang C, Kumagai K, Mabuchi Y, Yoshida K, Ikenaga T, Goto S. High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture. : 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006. 巻 2006. 2006
Yang, Changqi ; Kumagai, Kouichi ; Mabuchi, Yoshihiro ; Yoshida, Kenji ; Ikenaga, Takeshi ; Goto, Satoshi. / High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture. 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006. 巻 2006 2006.
@inproceedings{989d5590ae1f4118904795dcb840093f,
title = "High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture",
abstract = "The high performance chip design on H.264/AVC integer motion estimation is presented in this paper to satisfy the requirements from real-time HDTV video applications. Using a novel multi-chip architecture named System in Silicon (SiS), core ASIC and external DRAMs which are designed in different design rules are integrated onto a single chip to achieve the significantly wide word-width of 1024 bits and band-width of 25Gbps in logic-memory communication. In core's design, 2D PE array is adopted to avoid the broadcast signals which limit the circuit's speed and the delay registers which prevent the full hardware utilization. As the implementation, this chip is fabricated with 0.18μm technology (core) and 0.11μm technology (DRAM). The core size is 14.1×7.1 mm2, it contains 1966.1K logic gates and 22.5KB SRAM. It can work at the high operating clock frequency up to 200MHz and can process more than 263K macro blocks within one second. It is suitable to the application of HDTV video streams (1920×1088) at real time (30fps) and can be a useful part of multimedia system.",
author = "Changqi Yang and Kouichi Kumagai and Yoshihiro Mabuchi and Kenji Yoshida and Takeshi Ikenaga and Satoshi Goto",
year = "2006",
language = "English",
isbn = "300018726X",
volume = "2006",
booktitle = "25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006",

}

TY - GEN

T1 - High performance chip design on H.264/AVC integer motion estimation for 1080HDTV based on SiS multi-chip architecture

AU - Yang, Changqi

AU - Kumagai, Kouichi

AU - Mabuchi, Yoshihiro

AU - Yoshida, Kenji

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006

Y1 - 2006

N2 - The high performance chip design on H.264/AVC integer motion estimation is presented in this paper to satisfy the requirements from real-time HDTV video applications. Using a novel multi-chip architecture named System in Silicon (SiS), core ASIC and external DRAMs which are designed in different design rules are integrated onto a single chip to achieve the significantly wide word-width of 1024 bits and band-width of 25Gbps in logic-memory communication. In core's design, 2D PE array is adopted to avoid the broadcast signals which limit the circuit's speed and the delay registers which prevent the full hardware utilization. As the implementation, this chip is fabricated with 0.18μm technology (core) and 0.11μm technology (DRAM). The core size is 14.1×7.1 mm2, it contains 1966.1K logic gates and 22.5KB SRAM. It can work at the high operating clock frequency up to 200MHz and can process more than 263K macro blocks within one second. It is suitable to the application of HDTV video streams (1920×1088) at real time (30fps) and can be a useful part of multimedia system.

AB - The high performance chip design on H.264/AVC integer motion estimation is presented in this paper to satisfy the requirements from real-time HDTV video applications. Using a novel multi-chip architecture named System in Silicon (SiS), core ASIC and external DRAMs which are designed in different design rules are integrated onto a single chip to achieve the significantly wide word-width of 1024 bits and band-width of 25Gbps in logic-memory communication. In core's design, 2D PE array is adopted to avoid the broadcast signals which limit the circuit's speed and the delay registers which prevent the full hardware utilization. As the implementation, this chip is fabricated with 0.18μm technology (core) and 0.11μm technology (DRAM). The core size is 14.1×7.1 mm2, it contains 1966.1K logic gates and 22.5KB SRAM. It can work at the high operating clock frequency up to 200MHz and can process more than 263K macro blocks within one second. It is suitable to the application of HDTV video streams (1920×1088) at real time (30fps) and can be a useful part of multimedia system.

UR - http://www.scopus.com/inward/record.url?scp=34047146457&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34047146457&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:34047146457

SN - 300018726X

SN - 9783000187261

VL - 2006

BT - 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006

ER -