High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels

Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.

本文言語English
ホスト出版物のタイトルISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
ホスト出版物のサブタイトルNano-Bio Circuit Fabrics and Systems
ページ381-384
ページ数4
DOI
出版ステータスPublished - 2010 8 31
イベント2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
継続期間: 2010 5 302010 6 2

出版物シリーズ

名前ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
国/地域France
CityParis
Period10/5/3010/6/2

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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