HIGH PERFORMANCE LSI DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION.

Yukou Mochida*, Kazuo Murano, Toshitaka Tsuda, Hirohisa Gambe, Shigeru Fujii

*この研究の対応する著者

    研究成果: Article査読

    3 被引用数 (Scopus)

    抄録

    This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.

    本文言語English
    ページ(範囲)347-356
    ページ数10
    ジャーナルIEEE Journal on Selected Areas in Communications
    SAC-3
    2
    出版ステータスPublished - 1985 3

    ASJC Scopus subject areas

    • コンピュータ ネットワークおよび通信
    • 電子工学および電気工学

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