High performance networks on chip architecture with a new routing strategy for neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe

研究成果: Conference contribution

抄録

Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.

本文言語English
ホスト出版物のタイトルPrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
ページ347-350
ページ数4
DOI
出版ステータスPublished - 2010 12 20
イベント2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 - Shanghai, China
継続期間: 2010 9 222010 9 24

出版物シリーズ

名前PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

Conference

Conference2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010
CountryChina
CityShanghai
Period10/9/2210/9/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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