High performance NoC architecture for two hidden layers BP neural network

Yiping Dong, Takahiro Watanabe

研究成果: Conference contribution

抜粋

Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.

元の言語English
ホスト出版物のタイトル2008 International SoC Design Conference, ISOCC 2008
ページI269-I272
DOI
出版物ステータスPublished - 2008 12 1
イベント2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
継続期間: 2008 11 242008 11 25

出版物シリーズ

名前2008 International SoC Design Conference, ISOCC 2008
1

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
Korea, Republic of
Busan
期間08/11/2408/11/25

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

これを引用

Dong, Y., & Watanabe, T. (2008). High performance NoC architecture for two hidden layers BP neural network. : 2008 International SoC Design Conference, ISOCC 2008 (pp. I269-I272). [4815624] (2008 International SoC Design Conference, ISOCC 2008; 巻数 1). https://doi.org/10.1109/SOCDC.2008.4815624