High performance VLSI architecture of fractional motion estimation in H.264 for HDTV

J. Changqi Yang*, Satoshi Goto, Takeshi Ikenaga

*この研究の対応する著者

研究成果: Conference contribution

49 被引用数 (Scopus)

抄録

Fractional Motion Estimation (FME) on sub-pixels will occupy almost over 45% of the computation complexity of H.264 encoding process. Therefore a high performance VLSI architecture of FME is described in this paper to achieve the capacity of encoding the high-resolution real-time video stream for HDTV. Our design is improved from an existing work by involving a pipeline strategy in sub-pixel interpolation unit which can avoid the long delay paths in 6-tap ID FIR so as to increase the clock frequency up to 200MHz. Moreover, a 16-pixel search engine is adopted to remove the redundant interpolation area and parallelize the various block size search which can save more than half of the clock cycles in processing a macro block. Our design is implemented with only 189K gates at operating frequency of 200MHz in worst case(285MHz in typical case). It can provide the processing capacity of more than 250K MB/sec which is enough for 1080HD (1920×1088) video streams at frame rate of 30fps. It is a useful Intellectual Property (IP) design for multimedia system.

本文言語English
ホスト出版物のタイトルISCAS 2006
ホスト出版物のサブタイトル2006 IEEE International Symposium on Circuits and Systems, Proceedings
ページ2605-2608
ページ数4
出版ステータスPublished - 2006 12 1
イベントISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
継続期間: 2006 5 212006 5 24

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
国/地域Greece
CityKos
Period06/5/2106/5/24

ASJC Scopus subject areas

  • 電子工学および電気工学

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