This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard, which can support H.264 high profile features. Our goal is to design an Intra prediction engine for Ultra High Definition (UHD) Decoder (4Kx2K@60fps). The proposed architecture can achieve very stable throughput, which can process any H.264 intra prediction modes within 66 cycles. Comparing with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The proposed architecture can overlap data preparing time and prediction time, which can finish data loading and storing within 2 cycles pipeline stalls. We apply the combined module approach to achieve high throughput and low area cost for ultra high-definition video, which can support all H.264 features. The proposed architecture is verified to work at 81 MHz in a Xilinx V4 FPGA. It costs about 53.9K Gates by using TSMC 90nm and satisfies requirement of our UHD Decoder.
|ホスト出版物のタイトル||2009 International SoC Design Conference, ISOCC 2009|
|出版ステータス||Published - 2009|
|イベント||2009 International SoC Design Conference, ISOCC 2009 - Busan|
継続期間: 2009 11月 22 → 2009 11月 24
|Other||2009 International SoC Design Conference, ISOCC 2009|
|Period||09/11/22 → 09/11/24|
ASJC Scopus subject areas