High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada*, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

本文言語English
ホスト出版物のタイトル90 Symp VLSI Circuits
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ97-98
ページ数2
出版ステータスPublished - 1990
外部発表はい
イベント1990 Symposium on VLSI Circuits - Honolulu, HI, USA
継続期間: 1990 6月 71990 6月 9

Other

Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period90/6/790/6/9

ASJC Scopus subject areas

  • 工学(全般)

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