High-speed parallel sensing architecture for multi-megabit flash E2PROM's

Kazuo Kobayashi*, Takeshi Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Article査読

5 被引用数 (Scopus)

抄録

A high-speed parallel sensing architecture for high-density 5-V-only flash E2PROMs is described. A source-biasing technique enhances the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10-μA cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size.

本文言語English
ページ(範囲)79-83
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
25
1
DOI
出版ステータスPublished - 1990 2月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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