High-throughput decoder for low-density parity-check code

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2.

元の言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2006
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2006
出版者Institute of Electrical and Electronics Engineers Inc.
ページ112-113
ページ数2
ISBN(印刷物)0780394518, 9780780394513
DOI
出版物ステータスPublished - 2006 1 1
イベントASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
継続期間: 2006 1 242006 1 27

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2006

Conference

ConferenceASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Japan
Yokohama
期間06/1/2406/1/27

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • これを引用

    Ishikawa, T., Shimizu, K., Ikenaga, T., & Goto, S. (2006). High-throughput decoder for low-density parity-check code. : Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 112-113). [1594662] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1118299.1118332