High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

抄録

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

元の言語English
ホスト出版物のタイトル2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
ページ220-223
ページ数4
DOI
出版物ステータスPublished - 2008
イベント2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu
継続期間: 2008 4 232008 4 25

Other

Other2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Hsinchu
期間08/4/2308/4/25

Fingerprint

Message passing
Throughput
Parallel architectures
Sorting
Decoding

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Ji, W., Li, X., Ikenaga, T., & Goto, S. (2008). High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. : 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 220-223). [4542452] https://doi.org/10.1109/VDAT.2008.4542452

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. / Ji, Wen; Li, Xing; Ikenaga, Takeshi; Goto, Satoshi.

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 220-223 4542452.

研究成果: Conference contribution

Ji, W, Li, X, Ikenaga, T & Goto, S 2008, High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. : 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542452, pp. 220-223, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542452
Ji W, Li X, Ikenaga T, Goto S. High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. : 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 220-223. 4542452 https://doi.org/10.1109/VDAT.2008.4542452
Ji, Wen ; Li, Xing ; Ikenaga, Takeshi ; Goto, Satoshi. / High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. pp. 220-223
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