High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji*, Xing Li, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

抄録

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

本文言語English
ホスト出版物のタイトル2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
ページ220-223
ページ数4
DOI
出版ステータスPublished - 2008 9月 5
イベント2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China
継続期間: 2008 4月 232008 4月 25

出版物シリーズ

名前2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
国/地域Taiwan, Province of China
CityHsinchu
Period08/4/2308/4/25

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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