High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Tianruo Zhang, Shen Li, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

3 引用 (Scopus)

抄録

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

元の言語English
ホスト出版物のタイトル2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
ページ1245-1249
ページ数5
DOI
出版物ステータスPublished - 2008
イベント2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province
継続期間: 2008 5 252008 5 27

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Xiamen, Fujian Province
期間08/5/2508/5/27

Fingerprint

Throughput
Edge detection
High definition television
Image compression
Particle accelerators
Hardware
Processing

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

これを引用

Zhang, T., Li, S., Tian, G., Ikenaga, T., & Goto, S. (2008). High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. : 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1245-1249). [4657993] https://doi.org/10.1109/ICCCAS.2008.4657993

High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. / Zhang, Tianruo; Li, Shen; Tian, Guifen; Ikenaga, Takeshi; Goto, Satoshi.

2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249 4657993.

研究成果: Conference contribution

Zhang, T, Li, S, Tian, G, Ikenaga, T & Goto, S 2008, High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. : 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657993, pp. 1245-1249, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657993
Zhang T, Li S, Tian G, Ikenaga T, Goto S. High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. : 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249. 4657993 https://doi.org/10.1109/ICCCAS.2008.4657993
Zhang, Tianruo ; Li, Shen ; Tian, Guifen ; Ikenaga, Takeshi ; Goto, Satoshi. / High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. pp. 1245-1249
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