TY - GEN
T1 - High-throughput von Neumann post-processing for random number generator
AU - Zhang, Ruilin
AU - Chen, Sijia
AU - Wan, Chao
AU - Shinohara, Hirofumi
N1 - Funding Information:
This research is supported by ROHM Co., Ltd. and Kitakyushu Foundation for the Advancement of Industry, Science and Technology (FAIS).
Publisher Copyright:
© 2018 IEEE.
PY - 2018/6/5
Y1 - 2018/6/5
N2 - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
AB - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85049351907&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-DAT.2018.8373253
DO - 10.1109/VLSI-DAT.2018.8373253
M3 - Conference contribution
AN - SCOPUS:85049351907
T3 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
SP - 1
EP - 4
BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Y2 - 16 April 2018 through 19 April 2018
ER -