抄録
This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 |
| 出版社 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 1-4 |
| ページ数 | 4 |
| ISBN（電子版） | 9781538642603 |
| DOI | |
| 出版ステータス | Published - 2018 6 5 |
| イベント | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China 継続期間: 2018 4 16 → 2018 4 19 |
Other
| Other | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 |
|---|---|
| Country | Taiwan, Province of China |
| City | Hsinchu |
| Period | 18/4/16 → 18/4/19 |
ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Control and Optimization
- Hardware and Architecture
- Electrical and Electronic Engineering