抄録
This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 |
| 出版者 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 1-4 |
| ページ数 | 4 |
| ISBN（電子版） | 9781538642603 |
| DOI | |
| 出版物ステータス | Published - 2018 6 5 |
| イベント | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China 継続期間: 2018 4 16 → 2018 4 19 |
Other
| Other | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 |
|---|---|
| 国 | Taiwan, Province of China |
| 市 | Hsinchu |
| 期間 | 18/4/16 → 18/4/19 |
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ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Control and Optimization
- Hardware and Architecture
- Electrical and Electronic Engineering
これを引用
High-throughput von Neumann post-processing for random number generator. / Zhang, Ruilin; Chen, Sijia; Wan, Chao; Shinohara, Hirofumi.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.研究成果: Conference contribution
}
TY - GEN
T1 - High-throughput von Neumann post-processing for random number generator
AU - Zhang, Ruilin
AU - Chen, Sijia
AU - Wan, Chao
AU - Shinohara, Hirofumi
PY - 2018/6/5
Y1 - 2018/6/5
N2 - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
AB - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85049351907&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85049351907&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2018.8373253
DO - 10.1109/VLSI-DAT.2018.8373253
M3 - Conference contribution
AN - SCOPUS:85049351907
SP - 1
EP - 4
BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -