High-throughput von Neumann post-processing for random number generator

Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

研究成果: Conference contribution

3 引用 (Scopus)

抜粋

This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

元の言語English
ホスト出版物のタイトル2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
出版者Institute of Electrical and Electronics Engineers Inc.
ページ1-4
ページ数4
ISBN(電子版)9781538642603
DOI
出版物ステータスPublished - 2018 6 5
イベント2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China
継続期間: 2018 4 162018 4 19

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Taiwan, Province of China
Hsinchu
期間18/4/1618/4/19

    フィンガープリント

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Zhang, R., Chen, S., Wan, C., & Shinohara, H. (2018). High-throughput von Neumann post-processing for random number generator. : 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373253