High-throughput von Neumann post-processing for random number generator

Ruilin Zhang; Sijia Chen; Chao Wan; Hirofumi Shinohara

doi:10.1109/VLSI-DAT.2018.8373253

High-throughput von Neumann post-processing for random number generator

Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

大学院情報生産システム研究科

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

本文言語	English
ホスト出版物のタイトル	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	1-4
ページ数	4
ISBN（電子版）	9781538642603
DOI	https://doi.org/10.1109/VLSI-DAT.2018.8373253
出版ステータス	Published - 2018 6 5
イベント	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China 継続期間: 2018 4 16 → 2018 4 19

出版物シリーズ

名前	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Country	Taiwan, Province of China
City	Hsinchu
Period	18/4/16 → 18/4/19

ASJC Scopus subject areas

Safety, Risk, Reliability and Quality
Control and Optimization
Hardware and Architecture
Electrical and Electronic Engineering

文献へのアクセス

10.1109/VLSI-DAT.2018.8373253

他のファイルとリンク

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引用スタイル

Zhang, R., Chen, S., Wan, C., & Shinohara, H. (2018). High-throughput von Neumann post-processing for random number generator. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373253

High-throughput von Neumann post-processing for random number generator. / Zhang, Ruilin; Chen, Sijia; Wan, Chao; Shinohara, Hirofumi.

2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

研究成果: Conference contribution

Zhang, R, Chen, S, Wan, C & Shinohara, H 2018, High-throughput von Neumann post-processing for random number generator. in 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, Province of China, 18/4/16. https://doi.org/10.1109/VLSI-DAT.2018.8373253

Zhang R, Chen S, Wan C, Shinohara H. High-throughput von Neumann post-processing for random number generator. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). https://doi.org/10.1109/VLSI-DAT.2018.8373253

Zhang, Ruilin ; Chen, Sijia ; Wan, Chao ; Shinohara, Hirofumi. / High-throughput von Neumann post-processing for random number generator. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

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abstract = "This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.",

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