High-throughput von Neumann post-processing for random number generator

Ruilin Zhang; Sijia Chen; Chao Wan; Hirofumi Shinohara

doi:10.1109/VLSI-DAT.2018.8373253

High-throughput von Neumann post-processing for random number generator

Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

大学院情報生産システム研究科

研究成果: Conference contribution

3 引用（Scopus）

抜粋

This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

元の言語	English
ホスト出版物のタイトル	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
出版者	Institute of Electrical and Electronics Engineers Inc.
ページ	1-4
ページ数	4
ISBN（電子版）	9781538642603
DOI	https://doi.org/10.1109/VLSI-DAT.2018.8373253
出版物ステータス	Published - 2018 6 5
イベント	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China 継続期間: 2018 4 16 → 2018 4 19

Other

Other	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
国	Taiwan, Province of China
市	Hsinchu
期間	18/4/16 → 18/4/19

フィンガープリント

ASJC Scopus subject areas

Safety, Risk, Reliability and Quality
Control and Optimization
Hardware and Architecture
Electrical and Electronic Engineering

これを引用

Zhang, R., Chen, S., Wan, C., & Shinohara, H. (2018). High-throughput von Neumann post-processing for random number generator. ： 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373253

Zhang, R, Chen, S, Wan, C & Shinohara, H 2018, High-throughput von Neumann post-processing for random number generator. ： 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, Province of China, 18/4/16. https://doi.org/10.1109/VLSI-DAT.2018.8373253

@inproceedings{4ad6cf94ecfa4bd1ac700688c5cc3658,

title = "High-throughput von Neumann post-processing for random number generator",

abstract = "This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.",

author = "Ruilin Zhang and Sijia Chen and Chao Wan and Hirofumi Shinohara",

year = "2018",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2018.8373253",

language = "English",

pages = "1--4",

booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

}

TY - GEN

T1 - High-throughput von Neumann post-processing for random number generator

AU - Zhang, Ruilin

AU - Chen, Sijia

AU - Wan, Chao

AU - Shinohara, Hirofumi

PY - 2018/6/5

Y1 - 2018/6/5

N2 - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

AB - This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85049351907&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85049351907&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2018.8373253

DO - 10.1109/VLSI-DAT.2018.8373253

M3 - Conference contribution

AN - SCOPUS:85049351907

SP - 1

EP - 4

BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Y2 - 16 April 2018 through 19 April 2018

ER -

文献にアクセス

10.1109/VLSI-DAT.2018.8373253