A transparent polycrystalline diamond field-effect transistor (FET) was fabricated and measured in room temperature measurements, which reveals comparatively high maximum current density and high breakdown voltage of more than 1000 V. A harsh stress environment is proposed for simple and time-effective reliability stress measurement of the FET using a method of 50 continuous cycles of 500-V voltage stress. A 400-nm-thick Al2O3 counter-destructive passivation layer was implemented on the FET for the stress measurements. Devices with wide gate-drain length (LGD) retain their FET characteristics after the harsh stress measurements by only 50% reductions maximum current density.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering