High Voltage Stress Induced in Transparent Polycrystalline Diamond Field-Effect Transistor and Enhanced Endurance Using Thick Al2O3 Passivation Layer

Mohd Syamsul; Yuya Kitabayashi; Takuya Kudo; Daisuke Matsumura; Hiroshi Kawarada

doi:10.1109/LED.2017.2685081

High Voltage Stress Induced in Transparent Polycrystalline Diamond Field-Effect Transistor and Enhanced Endurance Using Thick Al₂O₃ Passivation Layer

Mohd Syamsul^*, Yuya Kitabayashi, Takuya Kudo, Daisuke Matsumura, Hiroshi Kawarada

^*この研究の対応する著者

基幹理工学部

研究成果 › 査読

20 被引用数 (Scopus)

抄録

A transparent polycrystalline diamond field-effect transistor (FET) was fabricated and measured in room temperature measurements, which reveals comparatively high maximum current density and high breakdown voltage of more than 1000 V. A harsh stress environment is proposed for simple and time-effective reliability stress measurement of the FET using a method of 50 continuous cycles of 500-V voltage stress. A 400-nm-thick Al₂O₃ counter-destructive passivation layer was implemented on the FET for the stress measurements. Devices with wide gate-drain length (L_GD) retain their FET characteristics after the harsh stress measurements by only 50% reductions maximum current density.

本文言語	English
論文番号	7882717
ページ（範囲）	607-610
ページ数	4
ジャーナル	IEEE Electron Device Letters
巻	38
号	5
DOI	https://doi.org/10.1109/LED.2017.2685081
出版ステータス	Published - 2017 5月

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/LED.2017.2685081

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引用スタイル

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abstract = "A transparent polycrystalline diamond field-effect transistor (FET) was fabricated and measured in room temperature measurements, which reveals comparatively high maximum current density and high breakdown voltage of more than 1000 V. A harsh stress environment is proposed for simple and time-effective reliability stress measurement of the FET using a method of 50 continuous cycles of 500-V voltage stress. A 400-nm-thick Al2O3 counter-destructive passivation layer was implemented on the FET for the stress measurements. Devices with wide gate-drain length (LGD) retain their FET characteristics after the harsh stress measurements by only 50% reductions maximum current density.",

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