Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

研究成果: Article

10 引用 (Scopus)

抜粋

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

元の言語English
記事番号6416957
ページ(範囲)924-931
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
48
発行部数4
DOI
出版物ステータスPublished - 2013 1 29
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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