The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1984 12 1|
ASJC Scopus subject areas