HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

T. Matsukawa, M. Inuishi, J. Mitsuhashi, M. Hirayama, K. Tsukamoto, S. Uoya, T. Yoshihara, H. Nakata

研究成果: Conference article

2 引用 (Scopus)

抜粋

The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.

元の言語English
ページ(範囲)647-650
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版物ステータスPublished - 1984 12 1

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

これを引用

Matsukawa, T., Inuishi, M., Mitsuhashi, J., Hirayama, M., Tsukamoto, K., Uoya, S., Yoshihara, T., & Nakata, H. (1984). HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. Technical Digest - International Electron Devices Meeting, 647-650.