Hybrid message-passing algorithm and architecture for decoding cyclic non-binary LDPC codes

Yichao Lu, Gang He, Guifen Tian, Satoshi Goto

研究成果: Article査読

抄録

Recently, non-binary low-density parity-check (NB-LDPC) codes starts to show their superiority in achieving significant coding gains when moderate codeword lengths are adopted. However, the overwhelming decoding complexity keeps NB-LDPC codes from being widely employed in modem communication devices. This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity. It achieves competitive error performance compared with conventional Min-max algorithm. Simulation result on a (255,174) cyclic code shows that this algorithm obtains at least 0.5 dB coding gain over other state-of-the-art low-complexity NB-LDPC decoding algorithms. A partial-parallel NB-LDPC decoder architecture for cyclic NB-LDPC codes is also developed based on this algorithm. Optimization schemes are employed to cut off hard decision symbols in RAMs and also to store only part of the reliability messages. In addition, the variable node units are redesigned especially for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

本文言語English
ページ(範囲)2652-2659
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E96-A
12
DOI
出版ステータスPublished - 2013

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 応用数学
  • 信号処理

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