This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seedgrowth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependencydriven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively.
|ホスト出版物のタイトル||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|出版ステータス||Published - 2008|
|イベント||GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL|
継続期間: 2008 3月 4 → 2008 3月 6
|Other||GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008|
|Period||08/3/4 → 08/3/6|
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