Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

    研究成果: Conference contribution

    2 引用 (Scopus)

    抜粋

    Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.

    元の言語English
    ホスト出版物のタイトルProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
    出版者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子版)9781479984831
    DOI
    出版物ステータスPublished - 2016 7 19
    イベント11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
    継続期間: 2015 11 32015 11 6

    Other

    Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
    China
    Chengdu
    期間15/11/315/11/6

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • これを引用

    Igarashi, K., Yanagisawa, M., & Togawa, N. (2016). Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. : Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7517027] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7517027