Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano; T. Matsumoto; S. Maeda; T. Iwamatsu; T. Kunikiyo; K. Nii; K. Yamamoto; Y. Yamaguchi; T. Ipposhi; S. Maegawa; M. Inuishi

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, M. Inuishi

研究成果: Conference article › 査読

27 被引用数 (Scopus)

抄録

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.

本文言語	English
ページ（範囲）	467-470
ページ数	4
ジャーナル	Technical Digest - International Electron Devices Meeting
出版ステータス	Published - 2000 12 1
外部発表	はい
イベント	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States 継続期間: 2000 12 10 → 2000 12 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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引用スタイル

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology. / Hirano, Y.; Matsumoto, T.; Maeda, S.; Iwamatsu, T.; Kunikiyo, T.; Nii, K.; Yamamoto, K.; Yamaguchi, Y.; Ipposhi, T.; Maegawa, S.; Inuishi, M.

In: Technical Digest - International Electron Devices Meeting, 01.12.2000, p. 467-470.

研究成果: Conference article › 査読

Hirano, Y. ; Matsumoto, T. ; Maeda, S. ; Iwamatsu, T. ; Kunikiyo, T. ; Nii, K. ; Yamamoto, K. ; Yamaguchi, Y. ; Ipposhi, T. ; Maegawa, S. ; Inuishi, M. / Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology. In: Technical Digest - International Electron Devices Meeting. 2000 ; pp. 467-470.

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abstract = "A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.",

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AU - Hirano, Y.

AU - Matsumoto, T.

AU - Maeda, S.

AU - Iwamatsu, T.

AU - Kunikiyo, T.

AU - Nii, K.

AU - Yamamoto, K.

AU - Yamaguchi, Y.

AU - Ipposhi, T.

AU - Maegawa, S.

AU - Inuishi, M.

PY - 2000/12/1

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