Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

T. Yamashita, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura

研究成果: Conference contribution

抄録

For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

本文言語English
ホスト出版物のタイトルIMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai
編集者Hiroshi Nozawa
出版社Institute of Electrical and Electronics Engineers Inc.
ページ123-124
ページ数2
ISBN(電子版)0780384237, 9780780384231
DOI
出版ステータスPublished - 2004
外部発表はい
イベント2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 - Kyoto, Japan
継続期間: 2004 7 262004 7 28

出版物シリーズ

名前IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai

Other

Other2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004
国/地域Japan
CityKyoto
Period04/7/2604/7/28

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル