Implementation of LDPC decoder for 802.16e

Xiao Peng; Satoshi Goto

doi:10.1109/ASICON.2009.5351628

Implementation of LDPC decoder for 802.16e

Xiao Peng^*, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

本文言語	English
ホスト出版物のタイトル	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
ページ	501-504
ページ数	4
DOI	https://doi.org/10.1109/ASICON.2009.5351628
出版ステータス	Published - 2009
イベント	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha 継続期間: 2009 10月 20 → 2009 10月 23

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
City	Changsha
Period	09/10/20 → 09/10/23

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASICON.2009.5351628

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title = "Implementation of LDPC decoder for 802.16e",

abstract = "The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.",

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language = "English",

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AB - The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

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BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

Implementation of LDPC decoder for 802.16e

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