Implementation of LDPC decoder for 802.16e

Xiao Peng, Satoshi Goto

研究成果: Conference contribution

4 引用 (Scopus)

抜粋

The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

元の言語English
ホスト出版物のタイトルASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
ページ501-504
ページ数4
DOI
出版物ステータスPublished - 2009
イベント2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
継続期間: 2009 10 202009 10 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
Changsha
期間09/10/2009/10/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Peng, X., & Goto, S. (2009). Implementation of LDPC decoder for 802.16e. : ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC (pp. 501-504). [5351628] https://doi.org/10.1109/ASICON.2009.5351628