Improved bipolar transistor model parameter generation technique for high-speed LSI design considering geometry-dependent parasitic elements

Yasunori Miyahara*, Minoru Nagata

*この研究の対応する著者

研究成果: Article査読

抄録

This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.

本文言語English
ページ(範囲)183-192
ページ数10
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E76-A
2
出版ステータスPublished - 1993 2
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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