In-situ timing monitoring methods for variation-resilient designs

研究成果: Conference contribution

抄録

With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.

本文言語English
ホスト出版物のタイトル2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ735-738
ページ数4
February
ISBN(電子版)9781479952304
DOI
出版ステータスPublished - 2015 2 5
イベント2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
継続期間: 2014 11 172014 11 20

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
番号February
2015-February

Other

Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
CountryJapan
CityIshigaki Island, Okinawa
Period14/11/1714/11/20

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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