Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Hiroshi Fuketa*, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

本文言語English
ホスト出版物のタイトルProceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOI
出版ステータスPublished - 2012 11月 26
外部発表はい
イベント34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
継続期間: 2012 9月 92012 9月 12

出版物シリーズ

名前Proceedings of the Custom Integrated Circuits Conference
ISSN(印刷版)0886-5930

Other

Other34th Annual Custom Integrated Circuits Conference, CICC 2012
国/地域United States
CitySan Jose, CA
Period12/9/912/9/12

ASJC Scopus subject areas

  • 電子工学および電気工学

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