Incremental placement and global routing algorithm for field-programmable gate arrays

Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki

    研究成果: Chapter

    4 引用 (Scopus)

    抄録

    Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

    元の言語English
    ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    出版場所Piscataway, NJ, United States
    出版者IEEE
    ページ519-526
    ページ数8
    出版物ステータスPublished - 1998
    イベントProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
    継続期間: 1998 2 101998 2 13

    Other

    OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
    Yokohama, Jpn
    期間98/2/1098/2/13

    Fingerprint

    Routing algorithms
    Field programmable gate arrays (FPGA)
    Specifications

    ASJC Scopus subject areas

    • Engineering(all)

    これを引用

    Togawa, N., Hagi, K., Yanagisawa, M., & Ohtsuki, T. (1998). Incremental placement and global routing algorithm for field-programmable gate arrays. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 519-526). Piscataway, NJ, United States: IEEE.

    Incremental placement and global routing algorithm for field-programmable gate arrays. / Togawa, Nozomu; Hagi, Kayoko; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 519-526.

    研究成果: Chapter

    Togawa, N, Hagi, K, Yanagisawa, M & Ohtsuki, T 1998, Incremental placement and global routing algorithm for field-programmable gate arrays. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, Piscataway, NJ, United States, pp. 519-526, Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, 98/2/10.
    Togawa N, Hagi K, Yanagisawa M, Ohtsuki T. Incremental placement and global routing algorithm for field-programmable gate arrays. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE. 1998. p. 519-526
    Togawa, Nozomu ; Hagi, Kayoko ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Incremental placement and global routing algorithm for field-programmable gate arrays. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. pp. 519-526
    @inbook{19ea654b5fa54c07a22eb3638be8406d,
    title = "Incremental placement and global routing algorithm for field-programmable gate arrays",
    abstract = "Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.",
    author = "Nozomu Togawa and Kayoko Hagi and Masao Yanagisawa and Tatsuo Ohtsuki",
    year = "1998",
    language = "English",
    pages = "519--526",
    booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
    publisher = "IEEE",

    }

    TY - CHAP

    T1 - Incremental placement and global routing algorithm for field-programmable gate arrays

    AU - Togawa, Nozomu

    AU - Hagi, Kayoko

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 1998

    Y1 - 1998

    N2 - Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

    AB - Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

    UR - http://www.scopus.com/inward/record.url?scp=0032218623&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0032218623&partnerID=8YFLogxK

    M3 - Chapter

    AN - SCOPUS:0032218623

    SP - 519

    EP - 526

    BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    PB - IEEE

    CY - Piscataway, NJ, United States

    ER -