抄録
An input buffer-type, high-capacity ATM switching system using schedule comparison is proposed for a high-speed ATM switching system whose internal link speed is equal to trunk speed. Its throughput, delay, and loss characteristics are evaluated. The schedule of the input buffer to send cells and that of the output to receive cells are compared to decide the timing to send a cell so that there exists only one cell bound for the same output line. The maximum throughput (outgoing trunk efficiency) is more than 0.9, and the mean delay is less than 10 cell times. Moreover, if a doubled transfer network is used, higher throughput can be achieved and the delay characteristic is almost equal to that with an ideal output buffer type. A comparison of the proposed scheme with the output buffer-type system under the same cell loss probability 10-5 reveals that the delay is almost the same and the required buffer size is one-third. This characteristic holds even if the system size is extended to 4096 lines; hence, a super high-capacity, high-speed switching system can be configured with the proposed system.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 17-25 |
| ページ数 | 9 |
| ジャーナル | Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) |
| 巻 | 74 |
| 発行部数 | 11 |
| 出版物ステータス | Published - 1991 11 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
これを引用
Input buffer-type ATM switching system using schedule comparison. / Fan, Ruixue; Akiyama, Minoru; Tanaka, Yoshiaki.
：: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 巻 74, 番号 11, 11.1991, p. 17-25.研究成果: Article
}
TY - JOUR
T1 - Input buffer-type ATM switching system using schedule comparison
AU - Fan, Ruixue
AU - Akiyama, Minoru
AU - Tanaka, Yoshiaki
PY - 1991/11
Y1 - 1991/11
N2 - An input buffer-type, high-capacity ATM switching system using schedule comparison is proposed for a high-speed ATM switching system whose internal link speed is equal to trunk speed. Its throughput, delay, and loss characteristics are evaluated. The schedule of the input buffer to send cells and that of the output to receive cells are compared to decide the timing to send a cell so that there exists only one cell bound for the same output line. The maximum throughput (outgoing trunk efficiency) is more than 0.9, and the mean delay is less than 10 cell times. Moreover, if a doubled transfer network is used, higher throughput can be achieved and the delay characteristic is almost equal to that with an ideal output buffer type. A comparison of the proposed scheme with the output buffer-type system under the same cell loss probability 10-5 reveals that the delay is almost the same and the required buffer size is one-third. This characteristic holds even if the system size is extended to 4096 lines; hence, a super high-capacity, high-speed switching system can be configured with the proposed system.
AB - An input buffer-type, high-capacity ATM switching system using schedule comparison is proposed for a high-speed ATM switching system whose internal link speed is equal to trunk speed. Its throughput, delay, and loss characteristics are evaluated. The schedule of the input buffer to send cells and that of the output to receive cells are compared to decide the timing to send a cell so that there exists only one cell bound for the same output line. The maximum throughput (outgoing trunk efficiency) is more than 0.9, and the mean delay is less than 10 cell times. Moreover, if a doubled transfer network is used, higher throughput can be achieved and the delay characteristic is almost equal to that with an ideal output buffer type. A comparison of the proposed scheme with the output buffer-type system under the same cell loss probability 10-5 reveals that the delay is almost the same and the required buffer size is one-third. This characteristic holds even if the system size is extended to 4096 lines; hence, a super high-capacity, high-speed switching system can be configured with the proposed system.
UR - http://www.scopus.com/inward/record.url?scp=0026250081&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026250081&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0026250081
VL - 74
SP - 17
EP - 25
JO - Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 8756-6621
IS - 11
ER -