Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Paper査読

3 被引用数 (Scopus)

抄録

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

本文言語English
ページ743-750
ページ数8
出版ステータスPublished - 2004 6 1
イベントProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
継続期間: 2004 1 272004 1 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
国/地域Japan
CityYokohama
Period04/1/2704/1/30

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

フィンガープリント

「Instruction set and functional unit synthesis for SIMD processor cores」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル