Integrated interlayer via planning and pin assignment for 3D ICs

Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto

    研究成果: Conference contribution

    3 被引用数 (Scopus)

    抄録

    As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs.

    本文言語English
    ホスト出版物のタイトルInternational Workshop on System Level Interconnect Prediction, SLIP
    ページ99-104
    ページ数6
    DOI
    出版ステータスPublished - 2009
    イベント2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 - San Francisco, CA
    継続期間: 2009 7 262009 7 27

    Other

    Other2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09
    CitySan Francisco, CA
    Period09/7/2609/7/27

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Applied Mathematics

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